Synchronous Up / Down Decade Counter (dual clock lines)
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the output change
coincidently with each other when so instructed by the steering logic. This mode of operation eliminates the output
counting spikes which are normally associated with asynchronous (ripple clock) counters. The outputs of the four
master-slave flip-flops are triggered by a low-to-high-level transition of either count (clock) input. The direction of
counting is determined by which count input is pulsed while the other count input is high. This counter is fully
programmable; that is, each output may be preset to either level by desired data at the data inputs while the load inputs
is low. The output will change to agree with the data inputs independently of the count pulses. This feature allows the
counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. A clear input
has been provided which forces all outputs to the low level when a high level is applied. The clear function is
independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive requirements.
This reduces the number of clock drivers, etc., required for long words. This counter was designed to be cascaded
without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up-and down-
The borrow output produces a pulse equal in width to the count-down input when the counter underflows. Similarly,
the carry output produces a pulse equal in width to the count up input when an overflow condition exists.
The counters can be easily cascaded by feeding the borrow and carry outputs to the count-down and count-up inputs
respectively of .the succeeding counter.
• Ordering Information
HD74LS192FPEL SOP-16 pin (JEITA)
Note: Please consult the sales office for the above package availability.
EL (2,000 pcs/reel)
Rev.2.00, Feb.18.2005, page 1 of 10