Dual Decade Counters
Mar 30, 2006
The HD74HC390 incorporate dual decade counters, each composed of a divide-by-two and a divide-by-five counter.
The divide-by-two and divide-by-five counters can be cascaded to form dual decade, dual bi-quinary, or various
combinations up to a single divide-by-100 counter.
The HD74HC390 is incremented on the high to low transition (negative edge) of the clock input, and each has an
independent clear input. When clear is set high all four bits of each counter are set to a low level. This enables count
truncation and allows the implementation of divide-by-N counter configurations.
• High Speed Operation: tpd (Clock A to QA) = 11 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
HD74HC390FPEL SOP-16 pin (JEITA)
Note: Please consult the sales office for the above package availability.
EL (2,000 pcs/reel)
A B Clear
1. H; High level, L; Low level, X; Irrelevant, Z; High impedance
Clear ÷2 and ÷5
Rev.2.00 Mar 30, 2006 page 1 of 6