Octal D-type Flip-Flops (with Enable)
Mar 30, 2006
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going
edge of the clock pulse if the enable input G is low. Clock triggering occurs at a particular voltage level and is not
directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level,
the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G
• High Speed Operation: tpd = 13 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
HD74HC377FPEL SOP-20 pin (JEITA)
HD74HC377RPEL SOP-20 pin (JEDEC)
Note: Please consult the sales office for the above package availability.
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
H X X Q0 Q0
L HH L
X L X Q0 Q0
Notes: 1. H ; High level, L ; Low level, X ; Irrelevant, ; Transition from L level to H level.
2. Q0 ; The level of Q before the indicated steady-state input conditions were established.
3. Q0 ; Complement of Q0 or level of Q before the indicated steady-state input conditions were established.
Rev.2.00 Mar 30, 2006 page 1 of 6