Dual 4-to-1-line Data Selectors/Multiplexers
Jan 31, 2006
Each of these data selectors/multiplexers contains inverters and drivers to supply full binary decoding data selection to
the AND-OR-invert gates. Separate strobe inputs (G) are provided for each of the two four-line sections.
The three-state outputs can interface with and drive data lines of bus-organized systems. With all but one of the
common output disabled (at a high-impedance state) the low-impedance of the single enable output will drive the bus
line to a high or low logic level. Each output has its own strobe (G). The output is disabled when its strobe is high.
• High Speed Operation: tpd (Data to Y) = 13 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
HD74HC353RPEL SOP-16 pin (JEDEC)
Note: Please consult the sales office for the above package availability.
EL (2,500 pcs/reel)
B A C0 C1 C2
L L LXX
L HX L X
H L XXH
Select inputs A and B are common to both sections
Rev.2.00 Jan 31, 2006 page 1 of 6