3-to-8-line Decoder/Demultiplexer with Address Latch
Jan 31, 2006
The HD74HC237 decodes a three-bit Address to one-of-eight active-high outputs. The device has a transparent latch
for storage of the Address. Two Chip Selects, one active-low and one active-high, are provided to facilitate the
demultiplexing, cascading, and chip-selecting functions.
The demultiplexing function is accomplished by using the Address inputs to select the desired device output, and then
by using one of the Chip Selects as a data input while holding the other one active.
The HD74HD237 is the noninverting version of the HD74HC137.
• High Speed Operation: tpd (Data to Y) = 19 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
HD74HC237FPEL SOP-16 pin (JEITA)
HD74HC237RPEL SOP-16 pin (JEDEC)
Note: Please consult the sales office for the above package availability.
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Rev.2.00 Jan 31, 2006 page 1 of 8