Parallel-load 8-bit Shift Register
Jan 31, 2006
This device is an 8-bit shift register with an output from the last stage. Data may be loaded into the register either in
parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in parallel. When the
Shift/Load input is high, the data is loaded serially on the rising edge of either clock inhibit or Clock. Clear is
asynchronous and active-low.
The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the
clock inputs to act as a clock inhibit.
• High Speed Operation: tpd (Clock to QH) = 14 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
HD74HC166FPEL SOP-16 pin (JEITA)
Note: Please consult the sales office for the above package availability.
EL (2,000 pcs/reel)
A ··· H
X XXXL L
X a ··· h a
H X H QAn
L X L QAn
QAo to QHo = Outputs remain unchanged.
QAn to QGn = Data shifted from the previous stage on a positive edge at the clock input.
H : High level
L : Low level
X : Irrelevant
Rev.3.00, Jan 31, 2006 page 1 of 6