288Mb: x9, x18, x36 CIO RLDRAM 2
AC and DC Operating Conditions
6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the
DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed
±2% of the DC value. Thus, from VDDQ/2, VREF is allowed ±2% VDDQ/2 for DC error and
an additional ±2% VDDQ/2 for AC noise. This measurement is to be taken at the nearest
VREF bypass capacitor.
7. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.
8. On-die termination may be selected using mode register bit 9 (see Mode Register Defini-
tion in Nonmultiplexed Address Mode). A resistance RTT from each data input signal to
the nearest VTT can be enabled.
RTT = 125–185Ω at 95°C TC.
9. IOH and IOL are defined as absolute values and are measured at VDDQ/2. IOH flows from
the device, IOL flows into the device.
10. If MRS bit A8 is 0, use RQ = 250Ω in the equation in lieu of presence of an external im-
pedance matched resistor.
11. For VOL and VOH, refer to the device HSPICE or IBIS driver models.
Table 9: Input AC Logic Levels
Notes 1–3 apply to entire table; unless otherwise noted: +0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V
Input high (logic 1) voltage
Input low (logic 0) voltage
VIH VREF + 0.2
VIL – VREF - 0.2
1. All voltages referenced to VSS (GND).
2. The AC and DC input level specifications are as defined in the HSTL standard (that is, the
receiver will effectively switch as a result of the signal crossing the AC input level and
will remain in that state as long as the signal does not ring back above [below] the DC
input LOW [HIGH] level).
3. The minimum slew rate for the input signals used to test the device is 2 V/ns in the
range between VIL(AC) and VIH(AC) (see Minimum Slew Rate figure below).
Figure 8: Minimum Slew Rate
rldram-2_cio_288mb.pdf - Rev. Q 10/15 EN
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