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MT49H16M18C Dataheets PDF



Part Number MT49H16M18C
Manufacturers Micron Technology
Logo Micron Technology
Description SIO RLDRAM 2
Datasheet MT49H16M18C DatasheetMT49H16M18C Datasheet (PDF)

SIO RLDRAM 2 MT49H16M18C – 16 Meg x 18 x 8 banks 288Mb: x18 SIO RLDRAM 2 Features Features • 533 MHz DDR operation (1.067 Gb/s/pin data rate) • 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency) • Organization – 16 Meg x 18 separate I/O – 8 banks • Cyclic bank switching for maximum bandwidth • Reduced cycle time (15ns at 533 MHz) • Nonmultiplexed addresses (address multiplexing option available) • SRAM-type interface • Programmable READ latency (RL), row cycle time, and burst sequence l.

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SIO RLDRAM 2 MT49H16M18C – 16 Meg x 18 x 8 banks 288Mb: x18 SIO RLDRAM 2 Features Features • 533 MHz DDR operation (1.067 Gb/s/pin data rate) • 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency) • Organization – 16 Meg x 18 separate I/O – 8 banks • Cyclic bank switching for maximum bandwidth • Reduced cycle time (15ns at 533 MHz) • Nonmultiplexed addresses (address multiplexing option available) • SRAM-type interface • Programmable READ latency (RL), row cycle time, and burst sequence length • Balanced READ and WRITE latencies in order to optimize data bus utilization • Data mask for WRITE commands • Differential input clocks (CK, CK#) • Differential input data clocks (DKx, DKx#) • On-die DLL generates CK edge-aligned data and output data clock signals • Data valid signal (QVLD) • 32ms refresh (8K refresh for each bank; 64K refresh command must be issued in total each 32ms) • HSTL I/O (1.5V or 1.8V nominal) • 25–60Ω matched impedance .


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