AS7C1025

March 2001 AS7C1025 AS7C31025 ® 5V/3.3V 128Kx8 CMOS SRAM (Revolutionary pinout) Features AS7C1025 (5V version) AS7C31025 (3.3V version) Industrial and commercial temperatures Organization: 131,072 words × 8 bits High speed - 12/15/20 ns address access time - 6,7,8 ns output enable access time Low power consumption: ACTIVE - 715 mW (AS7C1025) / max @ 12 ns (5V) - 360 mW (AS7C31025) / max @ 12 ns (3.3V) Low power consumption: STANDBY - 27.5 mW (AS7C1025) / max CMOS (5V) - 1.8 mW (AS7C31025) / max CMOS (3.3V) 2.0V data retention Easy memory expansion with CE, OE inputs Center power and ground TTL/LVTTL-compatible, three-state I/O JEDEC-standard packages - 32-pin, 300 mil SOJ - 32-pin, 400 mil SOJ - 32-pin TSOP II ESD protection ≥ 2000 volts Latch-up current ≥ 200 mA Logic block diagram Pin arrangement Row decoder Sense amp VCC GND Input buffer A0 A1 A2 A3 A4 512×256×8 Array A5 (1,048,576) A6 A7 A8 I/O7 I/O0 ...