NM24C03

NM24C03 C05 C09 C17 2K- 4K- 8K- 16K-Bit Serial EEPROM with Write Protect (I2C Synchronous 2-Wire Bus) January 1993 NM24C03 C05 C09 C17 2K- 4K- 8K- 16K-Bit Serial EEPROM with Write Protect (I2C Synchronous 2-Wire Bus) General Description The NM24C03 C05 C09 C17 devices are 2048 4096 8192 16 834 bits respectively of CMOS non-volatile electrically erasable memory These devices conform to all specifications in the I2C 2-wire protocol and are designed to minimize device pin count and simplify PC board layout requirements The upper half of the memory can be disabled (Write Protected) by connecting the WP pin to VCC This section of memory then becomes unalterable unless WP is switched to VSS This communication protocol uses CLOCK (SCL) and DATA I O (SDA) lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s) In addition this bus structure allows for a maximum of 16K of EEPROM memory This is supported by the NSC family in 2K 4K 8K ...