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BUK565-60A Dataheets PDF



Part Number BUK565-60A
Manufacturers NXP
Logo NXP
Description PowerMOS transistor Logic level FET
Datasheet BUK565-60A DatasheetBUK565-60A Datasheet (PDF)

Philips Semiconductors Product specification PowerMOS transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mount applications. The device is intended for use in Switched Mode Power Supplies (SMPS), motor control, welding, DC/DC and AC/DC converters, and in automotive and general purpose switching applications. BUK565-60A QUICK REFERENCE DATA SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-.

  BUK565-60A   BUK565-60A


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Philips Semiconductors Product specification PowerMOS transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mount applications. The device is intended for use in Switched Mode Power Supplies (SMPS), motor control, welding, DC/DC and AC/DC converters, and in automotive and general purpose switching applications. BUK565-60A QUICK REFERENCE DATA SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance; VGS = 5 V MAX. 60 39 125 175 0.042 UNIT V A W ˚C Ω PINNING - SOT404 PIN 1 2 3 mb gate drain source drain DESCRIPTION PIN CONFIGURATION mb SYMBOL d g 2 1 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR ±VGS ±VGSM ID ID IDM Ptot Tstg Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Non-repetitive gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage temperature Junction temperature CONDITIONS RGS = 20 kΩ tp ≤ 50 µs Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 60 60 15 20 39 28 156 125 175 175 UNIT V V V V A A A W ˚C ˚C THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. minimum footprint, FR4 board (see Fig 18). TYP. MAX. 50 1.2 UNIT K/W K/W February 1996 1 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET STATIC CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IDSS IGSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Zero gate voltage drain current Gate source leakage current Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA VDS = VGS; ID = 1 mA VDS = 60 V; VGS = 0 V; Tj = 25 ˚C VDS = 60 V; VGS = 0 V; Tj =125 ˚C VGS = ±15 V; VDS = 0 V VGS = 5 V; ID = 20 A MIN. 60 1.0 - BUK565-60A TYP. 1.5 1 0.1 10 0.035 MAX. 2.0 10 1.0 100 0.042 UNIT V V µA mA nA Ω DYNAMIC CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL gfs Ciss Coss Crss td on tr td off tf Ld Ls PARAMETER Forward transconductance Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance CONDITIONS VDS = 25 V; ID = 20 A VGS = 0 V; VDS = 25 V; f = 1 MHz VDD = 30 V; ID = 3 A; VGS = 5 V; RGS = 50 Ω; Rgen = 50 Ω Measured from upper edge of drain tab to centre of die Measured from source lead soldering point to source bond pad MIN. 11 TYP. 20 1450 500 220 25 120 160 110 2.5 7.5 MAX. 1750 600 275 40 150 220 145 UNIT S pF pF pF ns ns ns ns nH nH REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS IF = 39 A ; VGS = 0 V IF = 39 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 30 V MIN. TYP. 1.4 60 0.30 MAX. 39 156 2.0 UNIT A A V ns µC AVALANCHE LIMITING VALUE Tmb = 25 ˚C unless otherwise specified SYMBOL WDSS PARAMETER Drain-source non-repetitive unclamped inductive turn-off energy CONDITIONS ID = 39 A ; VDD ≤ 25 V ; VGS = 5 V ; RGS = 50 Ω MIN. TYP. MAX. 90 UNIT mJ February 1996 2 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET BUK565-60A 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating 10 Zth j-mb / (K/W) BUKx55-lv 1 D= 0.5 0.2 0.1 0.05 0.02 0 P D tp D= tp T t 1E+01 0.1 0.01 0 20 40 60 80 100 Tmb / C 120 140 160 180 0.001 1E-07 T 1E-05 1E-03 t/s 1E-01 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) ID% Normalised Current Derating Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T ID / A 10 7 VGS / V = 5 BUK555-50A 120 110 100 90 80 70 60 50 40 30 20 10 0 100 80 60 40 4 20 3 0 20 40 60 80 100 Tmb / C 120 140 160 180 0 0 2 4 VDS / V 6 8 10 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS RDS(ON) / Ohm 3 3.5 4 4.5 BUK555-50A 1000 ID / A BUK555-60 0.20 5 100 R ( DS ON )= V / DS ID A tp = 10 us 100 us 0.15 0.10 VGS / V = 0.05 7 10 0 0 20 40 ID / A 60 80 100 10 1 ms DC 10 ms 100 ms 1 1 10 VDS / V 100 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS February 1996 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET BUK565-60A .


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