SLA24C02

Standard EEPROM ICs SLx 24C01/02 1/2 Kbit (128/256 × 8 bit) Serial CMOS-EEPROM with I2C Synchronous 2-Wire Bus Data Sheet 1998-07-27 SLx 24C01/02 Revision History: Current Version: 1998-07-27 Previous Version: 06.97 Page Page Subjects (major changes since last revision) (in previous (in current Version) Version) 3 3 Text was changed to “Typical programming time 5 ms for up to 8 bytes”. 5 5 WP = VCC protects the upper half entire memory. 15 15 Figure 11: second command byte is a CSR and not CSW. 4, 5 4, 5 CS0, CS1 and CS2 were replaced by n.c. 5 – The paragraph “Chip Select (CS0, CS1, CS2)” was removed completely. 11, 12 11, 12 The erase/write cycle is finished latest after 10 8 ms. 19 19 “Capacitive load …” were added. 20 20 Some timings were changed. 20 20 The line “erase/write cycle” was removed. 20 20 Chapter 7.4 “Erase and Write Characteristics” has been added. I2C Bus Purchase of Siemens I2C components conveys the license under the Phil...