WESTCODE An IXYS Company

Fast Symmetrical Gate Turn-Off Thyristor type H0500KC25#

In addition to the turn-on time figures given in the characteristics data, the curves of figure 9 give the

relationship of tgt to di/dt and IGM. The data in the curves of figures 7 & 8, gives the turn-on losses both with

and without snubber discharge, a snubber of the form given in diagram 2 is assumed. Only typical losses

are given due to the large number of variables which effect Eon. It is unlikely that all negative aspects

would appear in any one application, so typical figures can be considered as worst case. Where the turn-

on loss is higher than the figure given it will in most cases be compensated by reduced turn-off losses, as

variations in processing inversely effect many parameters. For a worst case device, which would also

have the lowest turn-off losses, Eon would be 1.5x values given in the curves of figures 7 & 8. Turn-on

losses are measured over the integral period specified below:-

10 µs

Eon = ∫ iv.dt

0

The turn-on loss can be sub-divided into two component parts, firstly that associated with tgt and secondly

the contribution of the voltage tail. For this series of devices tgt contributes 50% and the voltage tail 50%

(These figures are approximate and are influenced by several second order effects). The loss during tgt is

greatly affected by gate current and as with turn-on time (figure 9), it can be reduced by increasing IGM.

The turn-on loss associated with the voltage tail is not effected by the gate conditions and can only be

reduced by limiting di/dt, where appropriate a turn-on snubber should be used. In applications where the

snubber is discharged through the GTO thyristor at turn-on, selection of discharge resistor will effect Eon.

The curves of figure 8 are given for a snubber as shown in diagram 2, with R=5Ω, this is the lowest

recommended value giving the highest Eon, higher values will reduce Eon.

2.7 Turn-off characteristics

The basic circuit used for the turn-off test is given in diagram 10. Prior to the negative gate pulse being

applied constant current, equivalent to ITGQ, is established in the DUT. The switch Sx is opened just before

DUT is gated off with a reverse gate pulse as specified in the characteristic/data curves. After the period

tgt voltage rises across the DUT, dv/dt being limited by the snubber circuit. Voltage will continue to rise

across DUT until Dc turns-on at a voltage set by the active clamp Cc, the voltage will be held at this value

until energy stored in Lx is depleted, after which it will fall to VDC .The value of Lx is selected to give

required VD Over the full tail time period. The overshoot voltage VDM is derived from Lc and forward voltage

characteristic of DC, typically VDM=1.2VD to 1.5VD depending on test settings. The gate is held reverse

biased through a low impedance circuit until the tail current is fully extinguished.

Lc

Dc

Sx RL

Lx Rs

CT Ds

Vd

i DX

Cs Cd

Gate- DUT

drive

Cc

Vc

RCD snubber

Diagram 10, Turn-off test circuit.

The definitions of turn-off parameters used in the characteristic data are given in diagram 11.

Data Sheet. Type H0500KC25# Issue 2

Page 7 of 15

August, 2004