P‐Channel Logic Level Enhancement Mode Field Effect Transistor
Product Summary:
BVDSS
‐20V
D
RDSON (MAX.)
...
P‐Channel Logic Level Enhancement Mode Field Effect
Transistor
Product Summary:
BVDSS
‐20V
D
RDSON (MAX.)
3.2mΩ
ID
‐100A
G
UIS, Rg 100% Tested
S
Pb‐Free Lead Plating & Halogen Free
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
EMF02P02H
LIMITS
UNIT
Gate‐Source Voltage
VGS ±12
Continuous Drain Current1 Pulsed Drain Current2
TC = 25 °C TC = 100 °C
ID IDM
‐100 ‐73 ‐400
Avalanche Current
IAS ‐100
Avalanche Energy Repetitive Avalanche Energy3
L = 0.1mH, ID=‐100A, RG=25Ω
L = 0.05mH
EAS EAR
500 250
Power Dissipation
TC = 25 °C TC = 100 °C
Operating Junction & Storage Temperature Range
PD Tj, Tstg
69 27 ‐55 to 150
100% UIS testing in condition of VD=‐15V, L=0.1mH, VG=‐5V, IL=‐70A, Rated VDS=‐20V ...
