N & P‐Channel Logic Level Enhancement Mode Field Effect Transistor
Product Summary:
N‐CH P‐CH
BVDSS RDSO...
N & P‐Channel Logic Level Enhancement Mode Field Effect
Transistor
Product Summary:
N‐CH P‐CH
BVDSS RDSON (MAX.)
100V ‐100V 150mΩ 250mΩ
ID 3A ‐2.5A
Pb‐Free Lead Plating & Halogen Free
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
Gate‐Source Voltage
VGS
Continuous Drain Current Pulsed Drain Current1
TA = 25 °C TA = 100 °C
Power Dissipation
TA = 25 °C TA = 100 °C
Operating Junction & Storage Temperature Range
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
SYMBOL
Junction‐to‐Case
RJC
Junction‐to‐Ambient3
RJA
1Pulse width limited by maximum junction temperature. 2Duty cycle 1% 362.5°C / W when mounted on a 1 in2 pad of 2 oz copper.
2013/10/8
ID IDM PD Tj, Tstg
TYPICAL
EMBA5...