Document
N & P‐Channel Logic Level Enhancement Mode Field Effect Transistor
Product Summary:
N‐CH P‐CH
BVDSS RDSON (MAX.)
20V ‐20V 30.5mΩ 100mΩ
ID 5A ‐3.2A
Pb‐Free Lead Plating & Halogen Free
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
Gate‐Source Voltage
VGS
Continuous Drain Current Pulsed Drain Current1
TA = 25 °C TA = 100 °C
Power Dissipation
TA = 25 °C TA = 70 °C
Operating Junction & Storage Temperature Range
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
SYMBOL
Junction‐to‐Ambient
RJA
1Pulse width limited by maximum junction temperature. 2Duty cycle 1%
2012/12/27
ID IDM PD Tj, Tstg
TYPICAL
EMF30C02K
LIMITS
N‐CH
P‐CH
±12 ±12
5 ‐3.2
3.5 ‐2.5
20 ‐12.8
1.25 .