STP3010

DATA SHEET STP3010 July 1997 TGX TurboGX™ Graphics Accelerator DESCRIPTION The STP3010 employs over 128,000 gates and implements an extended superset of previous GX architectures. This chip provides an integral SBus interface, VRAM (video random-access memory) controller, a high-performance math engine, plus a high-performance rendering (or drawing) engine. A complete graphics accelerator can be built utilizing this chip, a clock device, VRAM, and a RAMDAC. The STP3010 delivers an unparalleled level of integration that has allowed for its inclusion on a single-wide SBus card. These products also make multi-headed acceleration a cost-effective reality. In addition to the STP3010’s enhanced functionality, it offers high-resolution, off-screen memory, and multi-buffering capabilities. The STP3010 comes in a 223-pin ceramic pin grid array (CPGA) package. FEATURES 100 percent compatibility with previous GX implementations Complete graphics accelerator in a single chip—just a...