TurboGX™ Graphics Accelerator
The STP3010 employs over 128,000 gates and implements an extended superset of previous GX architectures.
This chip provides an integral SBus interface, VRAM (video random-access memory) controller, a high-per-
formance math engine, plus a high-performance rendering (or drawing) engine. A complete graphics
accelerator can be built utilizing this chip, a clock device, VRAM, and a RAMDAC.
The STP3010 delivers an unparalleled level of integration that has allowed for its inclusion on a single-wide
SBus card. These products also make multi-headed acceleration a cost-effective reality. In addition to the
STP3010’s enhanced functionality, it offers high-resolution, off-screen memory, and multi-buffering
The STP3010 comes in a 223-pin ceramic pin grid array (CPGA) package.
• 100 percent compatibility with previous GX implementations
• Complete graphics accelerator in a single chip—just add RAM, a RAMDAC, and a clock device
• Large-scale integration in 0.6-micron custom CMOS
• Over 128,000 gates (~500,000 transistors)
• Integral high-performance rendering engine (up to 1600 Mpixels/s)
• Integral high-performance math engine (up to 100 MFLOPS)
• Integral asynchronous SBus interface (rendering and math performance independent of SBus clock rate)
• 1-Mb, 2-Mb, and 4-Mb VRAM support
• Integral high-performance VRAM controller
• New block mode support for high-speed solid ﬁll
• Multi-vector processing capability for 2 vectors per command
• 8x16 Font FIFO
• FIFO and destination caches
• Multi-mode, multi-buffering support assuring MIT X11 compliance
• High-speed block copy for raster copies between buffers (eliminates visual anomalies, or tearing during double
• Off-screen rendering support (improves window system performance)
• Enhanced programmable timing logic with support for ﬂicker-free 76 Hz vertical refresh rates and multi-resolution
support including 1024x768, 1152x900, 1280x1024, and 1600x1280.
• Software driver for the device is included in Solaris 1.X and 2.X