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CY7C1248KV18
36-Mbit DDR II+ SRAM Two-Word Burst Architecture
Description
CY7C1248KV18/CY7C1250KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features ■ 36-Mbit density (2M × 18, 1M × 36) ■ 450 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferre...
Cypress Semiconductor
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CY7C1248KV18
36-Mbit DDR II+ SRAM Two-Word Burst Architecture
- Cypress Semiconductor
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