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CY7C2265XV18

Part Number	CY7C2265XV18
Manufacturer	Cypress Semiconductor
Description	36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
Published	Mar 14, 2017
Detailed Description	CY7C2263XV18 CY7C2265XV18 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 3...
Datasheet	CY7C2265XV18 PDF File

Overview

CY7C2263XV18 CY7C2265XV18 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.
5 Cycle Read Latency) with ODT 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.
5 Cycle Read Latency) with ODT Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 633 MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 1266 MHz) at 633 MHz ■ Available in 2.
5 clock cycle latency ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Data val...

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CY7C2265XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture - Cypress Semiconductor

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