72-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
CY7C1563XV18/CY7C1565XV18
72-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
72-Mbit QD...
Description
CY7C1563XV18/CY7C1565XV18
72-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
72-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
Features
■ Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions
■ 633 MHz Clock for High Bandwidth ■ Four-word Burst for Reducing Address Bus Frequency ■ Double Data Rate (DDR) Interfaces on both Read and Write
Ports (data transferred at 1266 MHz) at 633 MHz ■ Available in 2.5 Clock Cycle Latency ■ Two Input Clocks (K and K) for precise DDR Timing
❐ SRAM uses rising edges only ■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems ■ Data Valid Pin (QVLD) to indicate Valid Data on the Output ■ Single Multiplexed Address Input Bus latches Address Inputs
for Read and Write Ports ■ Separate Port selects for Depth Expansion ■ Synchronous Internally Self-timed Writes ■ QDR® II+ Xtreme operates with 2.5 cycle read latency when
DO...
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