CY7C1618KV18/CY7C1620KV18
144-Mbit DDR II SRAM Two-Word Burst Architecture
144-Mbit DDR II SRAM Two-Word Burst Architecture
Features
■ 144-Mbit density (8M × 18, 4M × 36) ■ 333 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at
666 MHz) at 333 MHz ■ Two input clocks (K an...
