18-Mbit Pipelined SRAM
CY7C1380DV33 CY7C1382DV33
18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM
18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM
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Description
CY7C1380DV33 CY7C1382DV33
18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM
18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM
Features
■ Supports bus operation up to 200 MHz ■ Available speed grades is 200 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V or 3.3 V I/O power supply ■ Fast clock-to-output times
❐ 3 ns (for 200 MHz device) ■ Provides high performance 3-1-1-1 access rate ■ User selectable burst counter supporting Intel Pentium®
interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed write ■ Asynchronous output enable ■ Single cycle chip deselect ■ CY7C1380DV33 is available in JEDEC-standard Pb-free
100-pin TQFP and 165-ball FBGA package and CY7C1382DV33 is available in 165-ball FBGA package ■ IEEE 1149.1 JTAG-Compatible Boundary Scan ■ ZZ sleep mode option
Functional Description
The CY7C1380DV33/CY7C1382DV33 SRAM integrates 524,288 × 36 an...
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