CY7C1614KV18

CY7C1625KV18 CY7C1612KV18 CY7C1614KV18 144-Mbit QDR® II SRAM Two-Word Burst Architecture 144-Mbit QDR® II SRAM Two-Word Burst Architecture Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 360-MHz clock for high bandwidth ■ Two-word burst on all accesses ■ Double data rate (DDR) interfaces on both read and write ports (data transferred at 720 MHz) at 360 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Single multiplexed address input bus latches address inputs for both read and write ports ■ Separate port selects for depth expansion ■ Synchronous internally self-timed writes ■ Quad data rate (QDR®) II operates with 1.5-cycle read latency when DOFF is asserted high ■ Operates similar to QDR I device with 1 cyc...