CY7C1463BV33
36-Mbit (2 M × 18) Flow-Through SRAM with NoBL™ Architecture
36-Mbit (2 M × 18) Flow-Through SRAM with NoBL™ Architecture
Features
■ No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
■ Supports up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock
■ Pin-compatible and fun...
