18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1371KV33 CY7C1371KVE33
CY7C1373KV33
18-Mbit (512K × 36/1M × 18) Flow-Through SRAM with NoBL™ Architecture (With ECC)...
Description
CY7C1371KV33 CY7C1371KVE33
CY7C1373KV33
18-Mbit (512K × 36/1M × 18) Flow-Through SRAM with NoBL™ Architecture (With ECC)
18-Mbit (512K × 36/1M × 18) Flow-through SRAM with NoBL™ Architecture (With ECC)
Features
■ No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles
■ Supports up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock
■ Pin-compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need
to use OE ■ Registered inputs for flow through operation ■ Byte write capability ■ 3.3 V/2.5 V I/O power supply (VDDQ) ■ Fast clock-to-output times
❐ 6.5 ns (for 133-MHz device) ■ Clock enable (CEN) pin to enable clock and suspend operation ■ Synchronous self-timed writes ■ Asynchronous output enable ■ Available in JEDEC-standard Pb-free 100-pin TQFP packages ■ Three chip enables for simple depth expansion ■ Automatic ...
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