MCM67W618

MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCM67W618 Product Preview 64K x 18 Bit Asynchronous Fast Static RAM With Address Latch and Byte Enable The MCM67W618 is a 1,179,648 bit static random access memory organized as 65,536 words of 18 bits, fabricated using Motorola's high-performance silicon-gate FN PACKAGE PLASTIC CASE 778 BiCMOS technology. The device integrates a 64K x 18 SRAM core with advanced peripheral circuitry consisting of address latches, active low chip enable, write en- able, separate upper and lower byte selects, and a fast output enable. This device has increased output drive capability supported by multiple power pins. PIN ASSIGNMENT Address latch enable (AL) is provided to simplify read and write cycles by guaranteeing address hold time in a simple fashion. When the address latch input is high, the address latch is in the transparent state. If the latch enable is tied ~;c~ ~~:~~v:~~o~~~::::r~::i:~na~;~~~~:~u:t:t:~M. When the address D~~~ Dual byte select...