MCM62981

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 64K X 4 Bit Fast Synchronous ParityRAMTM The MCM62981 is a 262,144 bit synchronous static random access memory organized as 65,536 words of 4 bits, fabricated using Motorola's high-performance silicon-gate CMOS technology. The device integrates a 64K x 4 SRAM core with advanced peripheral circuitry consisting of positive edge triggered registers on address and synchronous write enable inputs. Asynchronous controls include asynchronous write strobes and output enable (G).This device has increased output drive capability supported by multiple power pins. Four asynchronous write strobes (AWO - AW3) are provided to allow each bit position to be written individually, thereby simplifying the task of supporting byte parity. This x4 organized SRAM is ideally suited for parity on 32-bit words.The device is functionally similar to the MCM62980 and MCM62990 with the only difference being the individual bit write capablilty. Write cycles are differentiated...