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MOTOROLA
• SEMICONDUCTOR
TECHNICAL DATA
MCM62940B
Advance Information
32K x 9 Bit BurstRAMTM Synchronous Static RAM
With Burst Counter and Self-Timed Write
The MCM62940B is a 294,912 bit synchronous static random access memory
designed to provide a burstable, high-performance, secondary cache for the MC68040
and PowerPCTM microprocessors. It is organized as 32,768 words of 9 bits, fabricated
using Motorola's high-performance silicon-gate CMOS technology. The device inte-
grates input registers, a 2-bit counter, high speed SRAM, and high drive capability out-
puts onto a single monolithic circuit for reduced parts count implementation of cache
data RAM applications. Synchronous design allows precise cycle control with the use
of an external clock (K). CMOS circuitry reduces the overall power consumption of the
integrated functions for greater reliability.
A2
Addresses (AO - A14), data inputs (DOO - D08), and all control signals,
A3
except output enable (<3), are clock (.