EM47CM1688SBB

Revision History Revision 0.1 (Jun. 2012) -First release. EM47CM1688SBB Jun. 2012 1/38 www.eorex.com EM47CM1688SBB 1Gb (8M×8Bank×16) Double DATA RATE 3 SDRAM Features JEDEC Standard VDD/VDDQ = 1.5V±0.075V. All inputs and outputs are compatible with SSTL_15 interface. Fully differential clock inputs (CK, /CK) operation. Eight Banks Posted CAS by programmable additive latency: 0, CL-1 & CL-2 Bust length: 4 with Burst Chop (BC) and 8. CAS Write Latency (CWL): 5,6,7,8 Programmable CAS Latency (CL): 6, 7, 8, 9, 10, 11 Write Latency (WL) =Read Latency (RL) -1. Bi-directional Differential Data Strobe (DQS). Data inputs on DQS centers when write. Data outputs on DQS, /DQS edges when read. On chip DLL align DQ, DQS and /DQS transition with CK transition. DM mask write data-in at the both rising and falling edges of the data strobe. Sequential & Interleaved Burst type available both for 8 & 4 with BC. Multi Purpose Register...