EM44CM1688LBB

Revision History Revision 0.1 (Nov. 2010) -First release. EM44CM1688LBB Nov. 2010 1/29 www.eorex.com EM44CM1688LBB 1Gb (8M×8Bank×16) Double DATA RATE 2 SDRAM Features JEDEC Standard VDD/VDDQ = 1.8V±0.1V. All inputs and outputs are compatible with SSTL_18 interface. Fully differential clock inputs (CK, /CK) operation. Eight Banks Posted CAS Bust length: 4 and 8. Programmable CAS Latency (CL): 5 Programmable Additive Latency (AL): 0, 1, 2, 3, 4, 5 & 6. Write Latency (WL) =Read Latency (RL) -1. Read Latency (RL) = Programmable Additive Latency (AL) + CAS Latency (CL) Bi-directional Differential Data Strobe (DQS). Data inputs on DQS centers when write. Data outputs on DQS, /DQS edges when read. On chip DLL align DQ, DQS and /DQS transition with CK transition. DM mask write data-in at the both rising and falling edges of the data strobe. Sequential & Interleaved Burst type available. Off-Chip Driver (OCD) Impedance...