CD4078BMS

CD4078BMS December 1992 CMOS 8 Input NOR/OR Gate Pinout K ** 1 A 2 B 3 C 4 D 5 NC 6 VSS 7 Features High Voltage Type (20V Rating) Medium Speed Operation - tPHL, tPLH = 75ns (Typ.) at VDD = 10V Buffered Inputs and Output 5V, 10V and 15V Parametric Ratings Standardized, Symmetrical Output Characteristics 100% Tested for Quiescent Current at 20V Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” CD4078BMS TOP VIEW 14 VDD 13 J * 12 H 11 G 10 F 9 E 8 NC *J=A+B+C+D+E+F+G+H NC = NO CONNECTION ** K = A + B + C + D + E + F + G + H Functional Diagram A B C D 2 3 4 5 1 13 E F G H 9 10 11 12 J=A+B+C+D+E+F+G+H K=A+B+C+D+E+F+G+H 6, 8 = NO CONNECTION VDD = 14 VSS = 7 K J Description CD4078BMS NOR/OR Gate provides the system designer with direct implementation of the positive logic 8 input NOR and OR functions and supplements the existing family of CMOS gates. The CD4078BMS is supplied in these 14 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4Q H1B H3W Logic Diagram A 2 B 3 C 4 D 5 13 J E 9 1 K F 10 G 11 H 12 FIGURE 1. LOGIC DIAGRAM CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321...