CD4044BMS

DATASHEET CD4043BMS, CD4044BMS CMOS Quad 3 State R/S Latches FN3311 Rev 0.00 December 1992 Features High Voltage Types (20V Rating) Quad NOR R/S Latch- CD4043BMS Quad NAND R/S Latch - CD4044BMS 3 State Outputs with Common Output ENABLE Separate SET and RESET Inputs for Each Latch NOR and NAND Configuration 5V, 10V and 15V Parametric Ratings Standardized Symmetrical Output Characteristics 100% Tested for Quiescent Current at 20V Maximum Input Current of 1a at 18V Over Full Package-Temperature Range; - 100nA at 18V and 25oC Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Pinout Applications Holding Register in Multi-Register System Four Bits of Independent Storage with Output ENABLE Strobed Register General Digital Logic CD4043BMS for Positive Logic Systems CD4044BMS for Negative Logic Systems Description CD4043BMS types are quad cross-coupled 3-state CMOS NOR latches and the CD4044BMS types are quad cross-coupled 3state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic “1” or high on the ENABLE input connects the latch states to the Q outputs. A logic “0” or low on the ENABLE input disconnects the latch states from the Q outputs, results in an ope...