Document
CD4042BM CD4042BC Quad Clocked D Latch
March 1988
CD4042BM CD4042BC Quad Clocked D Latch
General Description
The CD4042BM CD4042BC quad clocked ‘‘D’’ latch is a monolithic complementary MOS (CMOS) integrated circuit constructed with P- and N-channel enhancement mode transistors The outputs Q and Q either latch or follow the data input depending on the clock level which is programmed by the polarity input For polarity e 0 the information present at the data input is transferred to Q and Q during 0 clock level and for polarity e 1 the transfer occurs during the 1 clock level When a clock transition occurs (positive for polarity e 0 and negative for polarity e 1) the information present at the input during the clock transition is retained at the outputs until an opposite clock transition occurs
Features
Y Y Y
Y Y Y
Wide supply voltage range High noise immunity Low power TTL compatibility Clock polarity control Fully buffered data inputs Q and Q outputs
3 0V to 15V 0 45 VDD (typ ) Fan out of 2 driving 74L or 1 driving 74LS
Connection Diagram
Dual-In-Line Package
Truth Table
Clock 0 L 1 K Polarity 0 0 1 1 Q D Latch D Latch
Order Number CD4042B
TL F 5966 – 1
Top View
Logic Diagrams
TL F 5966 – 2 TL F 5966 – 3
TL F 5966 – 4
C1995 National Semiconductor Corporation
TL F 5966
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings (Notes 1 and 2)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering 10 seconds)
b 0 5V to a 18V b 0 5V to VDD a 0 5V b 65 C to a 150 C
Recommended Operating Conditions (Note 2)
Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4042BM CD4042BC 3V to 15V 0V to VDD
b 55 C to a 125 C b 40 C to a 85 C
700 mW 500 mW 260 C
DC Electrical Characteristics CD4042BM (Note 2)
Symbol IDD Parameter Conditions
b 55 C a 25 C a 125 C
Units mA mA mA V V V V V V
Min Quiescent Device Current VDD e 5V VDD e 10V VDD e 15V Low Level Output Voltage
Max 1 2 4 0 05 0 05 0 05
Min
Typ 0 02 0 02 0 02 0 0 0
Max 1 2 4 0 05 0 05 0 05
Min
Max 30 60 120 0 05 0 05 0 05
VOL
lIOl k 1 mA VIH e VDD VIL e 0V VDD e 5V VDD e 10V VDD e 15V
VOH
High Level Output Voltage lIOl k 1 mA VIH e VDD VIL e 0V VDD e 5V 4 95 VDD e 10V 9 95 VDD e 15V 14 95 Low Level Input Voltage
4 95 9 95 14 95 15 30 40
5 10 15 2 25 45 6 75 15 30 40
4 95 9 95 14 95 15 30 40 35 70 11 0 0 36 09 24
b 0 36 b0 9 b2 4 b1 0
VIL
lIOl k 1 mA VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1V or 9V VDD e 15V VO e 1 5V or 13 5V lIOl k 1 mA VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1V or 9V VDD e 15V VO e 1 5V or 13 5V
35 70 11 0 0 64 16 42
b 0 64 b1 6 b4 2
V V V V V V mA mA mA mA mA mA
VIH
High Level Input Voltage
35 70 11 0 0 51 13 34
b 0 51 b1 3 b3 4 b0 1
2 75 55 8 25 0 88 2 25 88
b 0 88 b 2 25.