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CD4030C Dataheets PDF



Part Number CD4030C
Manufacturers National Semiconductor
Logo National Semiconductor
Description Quad EXCLUSIVE-OR Gate
Datasheet CD4030C DatasheetCD4030C Datasheet (PDF)

CD4030M CD4030C Quad EXCLUSIVE-OR Gate February 1988 CD4030M CD4030C Quad EXCLUSIVE-OR Gate General Description The EXCLUSIVE-OR gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and Pchannel enhancement mode transistors All inputs are protected against static discharge with diodes to VDD and VSS Applications Y Y Y Y Y Features Y Y Y Y Y Y Wide supply voltage range 3 0V to 15V Low power 100 nW (typ ) Medium speed tPHL e tPLH e 40 ns (typ ) operation at .

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CD4030M CD4030C Quad EXCLUSIVE-OR Gate February 1988 CD4030M CD4030C Quad EXCLUSIVE-OR Gate General Description The EXCLUSIVE-OR gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and Pchannel enhancement mode transistors All inputs are protected against static discharge with diodes to VDD and VSS Applications Y Y Y Y Y Features Y Y Y Y Y Y Wide supply voltage range 3 0V to 15V Low power 100 nW (typ ) Medium speed tPHL e tPLH e 40 ns (typ ) operation at CL e 15 pF 10V supply High noise immunity 0 45 VCC (typ ) Automotive Data terminals Instrumentation Medical electronics Industrial controls Remote metering Computers Schematic Diagram TL F 5961 – 1 Connection Diagram Dual-In-Line Package TL F 5961 – 2 Order Number CD4030 C1995 National Semiconductor Corporation TL F 5961 RRD-B30M105 Printed in U S A Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at Any Pin (Note 1) Operating Temperature Range CD4030M CD4030C VSS b0 3V to VSS a 15 5V b 55 C to a 125 C b 40 C to a 85 C Storage Temperature Range Power Dissipation (PD) Dual-In-Line Small Outline Operating VDD Range Lead Temperature (Soldering 10 seconds) b 65 C to a 150 C 700 mW 500 mW VSS a 3 0V to VSS a 15V 260 C DC Electrical Characteristics CD4030M Limits Symbol Parameter Conditions Min IL PD VOL VOH VNL VNH IDN IDP II Quiescent Device Current Quiescent Device Dissipation Package Output Voltage Low Level Output Voltage High Level Noise Immunity (All Inputs) Noise Immunity (All Inputs) Output Drive Current N-Channel (Note 2) Output Drive Current P-Channel (Note 2) Input Current VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10V VI e 0V or VI e VDD 4 95 9 95 15 30 14 29 0 75 15 b 0 45 b 0 95 b 55 C a 25 C a 125 C Units Max 30 60 150 600 0 05 0 05 mA mA mW mW V V V V V V V V mA mA mA mA pA Typ Max 05 10 25 10 0 05 0 05 Min Typ 0 005 0 01 0 025 01 0 0 Max 05 10 25 10 0 05 0 05 Min Typ 4 95 9 95 15 30 15 30 06 12 b0 3 b 0 65 50 10 2 25 45 2 25 45 12 24 b0 6 b1 3 4 95 9 95 14 29 15 30 0 45 09 b 0 21 b 0 45 10 DC Electrical Characteristics CD4030C Limits Symbol Parameter Conditions Min IL PD VOL VOH VNL VNH IDN IDP II Quiescent Device Current Quiescent Device Dissipation Package Output Voltage Low Level Output Voltage High Level Noise Immunity (All Inputs) Noise Immunity (All Inputs) Output Drive Current N-Channel (Note 2) Output Drive Current P-Channel (Note 2) Input Current VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10 V VI e 0V or VI e VDD 4 95 9 95 15 30 14 29 0 35 07 b 0 21 b 0 45 b 40 C a 25 C a 85 C Units Max 70 140 350 1 400 0 05 0 05 mA mA mW mW V V V V V V V V mA mA mA mA pA Typ Max 50 10 25 100 0 05 0 05 Min Typ 0 05 01 0 25 10 0 0 Max 50 10 25 100 0 05 0 05 Min Typ 4 95 9 95 15 30 15 30 03 06 b 0 15 b 0 32 50 10 2 25 45 2 25 45 12 24 b0 6 b1 3 4 95 9 95 14 29 15 30 0 25 05 b 0 12 b 0 25 10 2 AC Electrical Characteristics Symbol tPHL tPLH tTHL tTLH CI Parameter Propagation Delay Time Propagation Delay Time Transition Time High to Low Level Transition Time Low to High Level Input Capacitance CD4030M Conditions Min VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10V VI e 0V or VI e VDD Limits Typ 100 40 100 40 70 25 80 30 50 Max 200 100 200 100 150 75 150 75 ns ns ns ns ns ns ns ns pF Units AC Parameters are guaranteed by DC correlated testing AC Electrical Characteristics Symbol tPHL tPLH tTHL tTLH CI Parameter Propagation Delay Time Propagation Delay Time Transition Time High to Low Level Transition Time Low to High Level Input Capacitance CD4030C Conditions Min VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10V VI e 0V or VI e VDD Limits Typ 100 40 100 40 70 25 80 30 50 Max 300 150 300 150 300 150 300 150 ns ns ns ns ns ns ns ns pF Units AC Parameters are guaranteed by DC correlated testing Note 1 This device should not be connected to circuits with power on because high transient voltages may cause permanent damage Note 2 IDN and IDP are tested one output at a time Truth Table (For One of Four Identical Gates) A 0 1 0 1 B 0 0 1 1 J 0 1 1 0 Where ‘‘1’’ e High Level ‘‘0’’ e Low Level 3 CD4030M CD4030C Quad EXCLUSIVE-OR Gate Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number CD4030MJ or CD4030CJ NS Package Number J14A Molded Dual-In-Line Package (N) Order Number CD4030MN or CD4030CN NS Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL.


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