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CD4027BMS

CMOS Dual J-K Master-Slave Flip-Flop

Description

CD4027BMS December 1992 CMOS Dual J-K Master-Slave Flip-Flop Pinout CD4027BMS TOP VIEW Features High Voltage Type (20V Rating) Set - Reset Capability Static Flip-Flop Operation - Retains State Indeﬁnitely with Clock Level Either “High” or “Low” Medium Speed Operation - 16MHz (typ.) Clock Toggle Rate at 10V Standardized Symmetrical Output Characte...

Intersil Corporation

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