HY57V28820HCLT

HY57V28820HC(L)T 4Banks x 4M x 8bits Synchronous DRAM 0.1 : Hynix Change 0.2 : Burst read single write mode correction Rev. 0.2 / Aug. 2001 1 HY57V28820HC(L)T 4Banks x 4M x 8bits Synchronous DRAM DESCRIPTION The Hynix HY57V28820HC(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V28820HC(L)T is organized as 4banks of 4,194,304x8. HY57V28820HC(L)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequenti...