CD4023M CD4023C Triple 3-Input NAND Gate CD4025M CD4025C Triple 3-Input NOR Gate
February 1988
CD4023M CD4023C Triple ...
CD4023M CD4023C Triple 3-Input NAND Gate CD4025M CD4025C Triple 3-Input NOR Gate
February 1988
CD4023M CD4023C Triple 3-Input NAND Gate CD4025M CD4025C Triple 3-Input NOR Gate
General Description
These triple gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode
transistors All inputs are protected against static discharge with diodes to VDD and VSS
Features
Y Y Y Y
Wide supply voltage range High noise immunity 5V – 10V parametric ratings Low power
3 0V to 15V 0 45 VDD (typ )
Connection Diagrams
Dual-In-Line Packages CD4023M CD4023C CD4025M CD4025C
TL F 5955 – 1
TL F 5955 – 2
Top View Order Number CD4023 or CD4025
Top View
C1995 National Semiconductor Corporation
TL F 5955
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications
Voltage at Any Pin Operating Temperature Range CD4023M CD4025M CD4023C CD4025C VSSb to VDD a 0 3V
b 55 C to a 125 C b 40 C to a 85 C
Storage Temperature Range Power Dissipation (PD) Dual-In-Line Small Outline Operating VDD Range Lead Temperature (Soldering 10 seconds)
b 65 C to a 150 C
700 mW 500 mW VSS a 3 0V to VSS a 15V 260 C
DC Electrical Characteristics CD4023M
Symbol Parameter Conditions
CD4025M Limits
b 55 C a 25 C a 125 C
Units
Min IL PD VOL VOH VNL VNH IDN IDP IDN IDP II Quiescent Device Current Quie...