CD40174BMS

DATASHEET CD40174BMS CMOS Hex ‘D’-Type Flip-Flop Rev X.00 Jan 13, 2017 Features High Voltage Type (20V Rating) 5V, 10V and 15V Parametric Ratings Standardized, Symmetrical Output Characteristics 100% Tested for Quiescent Current at 20V Maximum Input Current of 1A at 18V Over Full Package Temperature Range, 100nA at 18V and +25oC Noise Margin (Over full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V Meets All Requirements of JEDEC Tentative Standard No. 13A, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Pinout CD40174BMS TOP VIEW CLEAR 1 Q1 2 D1 3 D2 4 Q2 5 D3 6 Q3 7 VSS 8 16 VDD 15 Q6 14 D6 13 D5 12 Q5 11 D4 10 Q4 9 CLOCK Applications Shift Registers Buffer/Storage Registers Functional Diagram D1 3 Pattern Generators Description D2 4 CD40174BMS consists of six identical ‘D’-Type flip-flops having independent DATA inputs. The CLOCK and CLEAR inputs are common to all six units. Data is transferred to the Q outputs on the positive going transition of the clock pulse. All six flip-flops are simultaneously reset by a low level on the CLEAR input. The CD40174BMS is supplied in these 16 lead outline packages: Braze Seal DIP H4T D3 6 D4 11 D5 13 Frit Seal DIP H1E Ceramic Flatpack H6W D5 14 CLOCK 9 CLEAR 1 VSS = 8 VDD = 16 F/F1 F/F2 F/F3 F/F4 F/F5 F/F6 2 Q1 5 Q2 7 Q3 10 Q4 12 Q5 15 Q6 Rev X.00 Jan 13, 2017 Page 1 of 8 CD40174BMS Specifications CD40174BMS Absolute Maximum Ratings DC...