CD40104BMS

CD40104BMS, CD40194BMS December 1992 CMOS 4-Bit Bidirectional Universal Shift Register Pinouts OUTPUT ENABLE 1 SHIFT RIGHT IN 2 D0 3 D1 4 D2 5 D3 6 SHIFT LEVEL IN 7 VSS 8 Features High Voltage Type (20V Rating) Medium Speed fCL = 12MHz (typ.) at VDD = 10V Fully Static Operation Synchronous Parallel or Serial Operation Three State Outputs (CD40104BMS) Asynchronous Master Reset (CD40194BMS) 5V, 10V and 15V Parametric Ratings Standardized Symmetrical Output Characteristics Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” CD40104BMS TOP VIEW 16 VDD 15 Q0 14 Q1 13 Q2 12 Q3 11 CLOCK 10 SELECT 1 9 SELECT 0 Applications Arithmetic Unit Bus Registers Serial/Parallel Conversions General Purpose Register for Bus Organized Systems General Purpose Registers RESET 1 SHIFT RIGHT IN 2 D0 3 D1 4 D2 5 D3 6 SHIFT LEVEL IN 7 VSS 8 CD40194BMS TOP VIEW 16 VDD 15 Q0 14 Q1 13 Q2 12 Q3 11 CLOCK 10 SELECT 1 9 SELECT 0 Description The CD40104BMS is a universal shift register featuring parallel inputs, parallel outputs, SHIFT RIGHT and SHIFT LEFT serial inputs, and a high impedance third output state allowing the device to be used in bus organized systems. In the parallel load mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the CLOCK input. During loading, serial data flow is inhibited. Shift right and shift left ar...