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CD4002BMS Dataheets PDF



Part Number CD4002BMS
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description CMOS NOR Gate
Datasheet CD4002BMS DatasheetCD4002BMS Datasheet (PDF)

CD4000BMS, CD4001BMS CD4002BMS, CD4025BMS November 1994 CMOS NOR Gate Pinouts CD4000BMS TOP VIEW NC 1 NC 2 A 3 B 4 C 5 H=A+B+C 6 VSS 7 14 VDD 13 F 12 E 11 D 10 K = D + E + F 9 L=G 8 G NC = NO CONNECTION Features • High-Voltage Types (20V Rating) • Propagation Delay Time = 60ns (typ.) at CL = 50pF, VDD = 10V • Buffered Inputs and Outputs • Standard Symmetrical Output Characteristics • 100% Tested for Maximum Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Maximum Input Current o.

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CD4000BMS, CD4001BMS CD4002BMS, CD4025BMS November 1994 CMOS NOR Gate Pinouts CD4000BMS TOP VIEW NC 1 NC 2 A 3 B 4 C 5 H=A+B+C 6 VSS 7 14 VDD 13 F 12 E 11 D 10 K = D + E + F 9 L=G 8 G NC = NO CONNECTION Features • High-Voltage Types (20V Rating) • Propagation Delay Time = 60ns (typ.) at CL = 50pF, VDD = 10V • Buffered Inputs and Outputs • Standard Symmetrical Output Characteristics • 100% Tested for Maximum Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Package-Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standards No. 13B, “Standard Specifications for Description of “B” Series CMOS Device’s CD4001BMS TOP VIEW A 1 B 2 J=A+B 3 K=C+D 4 C 5 D 6 VSS 7 14 VDD 13 H 12 G 11 M = G + H 10 L = E + F 9 F 8 E NC = NO CONNECTION Description CD4000BMS CD4001BMS CD4002BMS CD4025BMS - Dual 3 Plus Inverter - Quad 2 Input - Dual 4 Input - Triple 3 Input CD4002BMS TOP VIEW J=A+B+C+D 1 A 2 B 3 C 4 D 5 NC 6 VSS 7 14 VDD 13 K = E + F + G + H 12 H 11 G 10 F 9 E 8 NC NC = NO CONNECTION CD4000BMS, CD4001BMS, CD4002BMS, and CD4025BMS NOR gates provide the system designer with direct implementation of the NOR function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. The CD4000BMS, CD4001BMS, CD4002BMS and the CD4025BMS is supplied in these 14 lead outline packages: CD4000B CD4001B CD4002B CD4025B Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4X H1B H3W H4Q H1B H3W H4Q H1B H3W H4Q H1B H3W A 1 B 2 D 3 E 4 F 5 K=D+E+F 6 VSS 7 CD4025BMS TOP VIEW 14 VDD 13 G 12 H 11 I 10 L = G + H + I 9 J=A+B+C 8 C NC = NO CONNECTION CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 File Number 3289 7-649 CD4000BMS, CD4001BMS, CD4002BMS, CD4025BMS Functional Diagrams J=A+B M=G+H NC NC A B C H VSS 1 K=D+E+F 14 VDD F E D K L G A 1 2 3 14 13 12 VDD 2 13 B H 3 12 J G K=C+D 4 11 K 4 5 6 11 M 5 H=A+B+C 10 9 C 10 9 8 L=E+F L 6 D F 7 L=G 8 VSS 7 E CD4000BMS CD4001BMS J A B C D NC VSS 1 J=A+B+C+D 14 13 12 11 10 9 K=E+F+G+H VDD K H G F E NC A 1 14 VDD 2 3 4 5 6 7 B 2 L=G+H+I 13 G D 3 12 H E 4 11 I F 5 10 9 K=D+E+F L J K 6 8 VSS 7 J=A+B+C 8 C CD4002BMS CD4025BMS 7-650 Specifications CD4000BMS, CD4001BMS, CD4002BMS, CD4025BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 .


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