DM54LS461

DM54LS461 DM74LS461 Octal Counter July 1989 DM54LS461 DM74LS461 Octal Counter General Description The LS461 is an 8-bit synchronous counter with parallel load clear and hold capability Two function select inputs (I0 I1) provide one of four operations which occur synchronously on the rising edge of the clock (CK) The LOAD operation loads the inputs (D7 – D0) into the output register (Q7 – Q0) The CLEAR operation resets the output register to all LOWs The HOLD operation holds the previous value regardless of clock transitions The INCREMENT operation adds one to the output register when the carry-in input is TRUE (CI e LOW) otherwise the operation is a HOLD The carry-out (CO) is TRUE (CO e LOW) when the output register (Q7 – Q0) is all HIGHs otherwise FALSE (CO e HIGH) The output register (Q7 – Q0) is enabled when OE is LOW and disabled (HI-Z) when OE is HIGH The output drivers will sink the 24 mA required for many bus interface standards Connection Diagram Two or more LS461 o...