82P33724

Port Synchronizer for IEEE 1588 and Synchronous Ethernet 82P33724 Short Form Datasheet This is a short form datasheet and is intended to provide an overview only. Additional details are available from IDT. Contact information may be found on the last page. HIGHLIGHTS DPLL1 and DPLL2 can be used on line cards to manage the generation of synchronous port clocks and IEEE 1588 synchronization signals based on multiple system backplane references DPLL3 can be used on line cards to select incoming line clocks for use on system backplanes; it can also be used for general purpose timing applications APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to 20 MHz) for: 1000BASE-T and 1000BASE-X ports and to generate IEEE 1588 time stamp clocks and 1 pulse per second (PPS) signals Fractional-N input dividers support a wide range of reference frequencies The device can be configured from an external EEPROM after reset FEATURES Differential reference inputs (IN1...