CY7C1305BV25

CY7C1305BV25 CY7C1307BV25 18-Mbit Burst of 4 Pipelined SRAM with QDR™ Architecture Features Functional Description Separate independent Read and Write data ports Supports concurrent transactions 167-MHz clock for high bandwidth 2.5 ns Clock-to-Valid access time 4-Word Burst for reducing the address bus frequency Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 333 MHz) @167 MHz Two input clocks (K and K) for precise DDR timing SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches. Single multiplexed address input bus latches address inputs for both Read and Write ports Separate Port Selects for depth expansion Synchronous internally self-timed writes 2.5V core power supply with HSTL Inputs and Outputs Available in 165-ball FBGA package (13 x 15 x 1.4 mm) Variable drive HSTL output buffers Expanded HSTL output voltage...