1.8 V synchronous pipelined SRAM
CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read...
Description
CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
Features
■ 36-Mbit density (4 M × 8, 4 M × 9, 2 M × 18, 1 M × 36) ■ 550 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces
(data transferred at 1100 MHz) at 550 MHz ■ Available in 2.5 clock cycle latency ■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems ■ Data valid pin (QVLD) to indicate valid data on the output ■ Synchronous internally self-timed writes ■ DDR II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH ■ Operates similar to DDR I device with 1 Cycle Read Latency
when DOFF is asserted LOW ■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD[1]
❐ Supports both 1.5 V an...
Similar Datasheet