36Mb S/DCD Sync Burst SRAMs
Preliminary GS832218(B/E)/GS832236(B/E)/GS832272(C)
119-, 165-, & 209-Pin BGA Commercial Temp Industrial Temp
2M x 18,...
Description
Preliminary GS832218(B/E)/GS832236(B/E)/GS832272(C)
119-, 165-, & 209-Pin BGA Commercial Temp Industrial Temp
2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
250 MHz–133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O
Features
FT pin for user-configurable flow through or pipeline operation Single/Dual Cycle Deselect selectable IEEE 1149.1 JTAG-compatible Boundary Scan ZQ mode pin for user-selectable high/low output drive 2.5 V +10%/–10% core power supply 3.3 V +10%/–10% core power supply 2.5 V or 3.3 V I/O supply LBO pin for Linear or Interleaved Burst mode Internal input resistors on mode pins allow floating mode pins Default to SCD x18/x36 Interleaved Pipeline mode Byte Write (BW) and/or Global Write (GW) operation Internal self-timed write cycle Automatic power-down for portable applications JEDEC-standard 119-, 165-, and 209-bump BGA package
Functional Description
Applications The GS832218/36/72 is a 37,748,736-bit...
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