GS4288C36GL

GS4288C09/18/36L 144-Ball BGA Commercial Temp Industrial Temp 32M x 9, 16M x 18, 8M x 36 288Mb CIO Low Latency DRAM (LLDRAM) II 533 MHz–300 MHz 2.5 V VEXT 1.8 V VDD 1.5 V or 1.8 V VDDQ Features Pin- and function-compatible with Micron RLDRAM® II 533 MHz DDR operation (1.067Gb/s/pin data rate) 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency) 8M x 36, 16M x 18, and 32M x 9 organizations available 8 internal banks for concurrent operation and maximum bandwidth Reduced cycle time (15 ns at 533 MHz) Address Multiplexing (Nonmultiplexed address option available) SRAM-type interface Programmable Read Latency (RL), row cycle time, and burst sequence length Balanced Read and Write Latencies in order to optimize data bus utilization Data mask for Write commands Differential input clocks (CK, CK) Differential input data clocks (DKx, DKx) On-chip DLL generates CK edge-aligned data and output data clock signals Data vali...