GS8662DT11BD

165-Bump BGA Commercial Temp Industrial Temp GS8662DT20/38BD-550/500/450/400/350 GS8662DT06/11BD-500/450/400/350 72Mb SigmaQuad-II+TM Burst of 4 SRAM 550 MHz–350 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features 2.5 Clock Latency Simultaneous Read and Write SigmaQuad™ Interface JEDEC-standard pinout and package Dual Double Data Rate interface Byte Write controls sampled at data-in time Burst of 4 Read and Write Dual-Range On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) intputs 1.8 V +100/–100 mV core power supply 1.5 V or 1.8 V HSTL Interface Pipelined read operation Fully coherent read and write pipelines ZQ pin for programmable output drive strength Data Valid Pin (QVLD) Support IEEE 1149.1 JTAG-compliant Boundary Scan 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package RoHS-compliant 165-bump BGA package available SigmaQuad-II™ Family Overview The GS8662DT06/11/20/38BD are built in compliance with the SigmaQuad-II+ SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. The GS8662DT06/11/20/38BD SigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes The GS8662DT06/11/20/38BD SigmaQuad-II+ SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock i...