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GS81302R09E Dataheets PDF



Part Number GS81302R09E
Manufacturers GSI Technology
Logo GSI Technology
Description 144Mb SigmaDDR-II Burst of 4 SRAM
Datasheet GS81302R09E DatasheetGS81302R09E Datasheet (PDF)

GS81302R08/09/18/36E-375/350/333/300/250 165-Bump BGA Commercial Temp Industrial Temp 144Mb SigmaDDRTM-II Burst of 4 SRAM 375 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write (x36 and x18) and Nybble Write (x8) function • Burst of 4 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation wit.

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GS81302R08/09/18/36E-375/350/333/300/250 165-Bump BGA Commercial Temp Industrial Temp 144Mb SigmaDDRTM-II Burst of 4 SRAM 375 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write (x36 and x18) and Nybble Write (x8) function • Burst of 4 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb devices • 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available SigmaDDR™ Family Overview The GS81302R08/09/18/36E are built in compliance with the SigmaDDR-II SRAM pinout standard for Common I/O synchronous SRAMs. They are 150,994,944-bit (144Mb) SRAMs. The GS81302R08/09/18/36E SigmaDDR-II SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes The GS81302R08/09/18/36E SigmaDDR-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Each internal read and write operation in a SigmaDDR-II B4 RAM is four times wider than the device I/O bus. An input data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced from a single memory array read and then route it to the appropriate output drivers as needed. When a new address is loaded into a x18 or x36 version of the part, A0 and A1 are used to initialize the pointers that control the data multiplexer / de-multiplexer so the RAM can perform "critical word first" operations. From an external address point of view, regardless of the starting point, the data transfers always follow the same linear sequence {00, 01, 10, 11} or {01, 10, 11, 00} or {10, 11, 00, 01} or {11, 00, 01, 10} (where the digits shown represent A1, A0). Unlike the x18 and x36 versions, the input and output data multiplexers of the x8 and x9 versions are not preset by address inputs and therefore do not allow "critical word first" operations. The address fields of the x8 and x9 SigmaDDR-II B4 RAMs are two address pins less than the advertised index depth (e.g., the 16M x 8 has a 4M addressable index, and A0 and A1 are not accessible address pins). Parameter Synopsis tKHKH tKHQV -375 2.66 ns 0.45 ns -350 2.86 ns 0.45 ns -333 3.0 ns 0.45 ns -300 3.3 ns 0.45 ns -250 4.0 ns 0.45 ns Rev: 1.03b 12/2011 1/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS81302R08/09/18/36E-375/350/333/300/250 4M x 36 SigmaDDR-II SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ SA SA R/W BW2 K BW1 LD SA SA CQ B NC DQ27 DQ18 SA BW3 K BW0 SA NC/SA (288Mb) NC DQ8 C NC NC DQ28 VSS SA SA0 SA1 VSS NC DQ17 DQ7 D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16 E NC NC DQ20 VDDQ VSS VSS VSS VDDQ NC DQ15 DQ6 F NC DQ30 DQ21 VDDQ VDD VSS VDD VDDQ NC NC DQ5 G NC DQ31 DQ22 VDDQ VDD VSS VDD VDDQ NC NC DQ14 H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC DQ32 VDDQ VDD VSS VDD VDDQ NC DQ13 DQ4 K NC NC DQ23 VDDQ VDD VSS VDD VDDQ NC DQ12 DQ3 L NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC NC DQ2 M NC NC DQ34 VSS VSS VSS VSS VSS NC DQ11 DQ1 N NC DQ35 DQ25 VSS SA SA SA VSS NC NC DQ10 P NC NC DQ26 SA SA C SA SA NC DQ9 DQ0 R TDO TCK SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch Notes: 1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to DQ27:DQ35. 2. B9 is the expansion address. Rev: 1.03b 12/2011 2/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS81302R08/09/18/36E-375/350/333/300/250 8M x 18 SigmaDDR-II SRAM—Top View 123456789 A CQ SA SA R/W BW1 K SA LD SA B NC DQ9 NC SA NC/SA (288Mb) K BW0 SA NC C NC NC NC VSS SA SA0 SA1 VSS NC D NC NC DQ10 VSS VSS VSS VSS VSS NC E NC NC DQ11 VDDQ VSS VSS VSS VDDQ NC F NC DQ12 NC VDDQ VDD VSS VDD VDDQ NC G .


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