GS81302TT11GE

GS81302TT06/11/20/38E-500/450/400/350 165-Bump BGA Commercial Temp Industrial Temp 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 500 MHz–350 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features 2.5 Clock Latency Simultaneous Read and Write SigmaDDRTM Interface JEDEC-standard pinout and package Double Data Rate interface Byte Write controls sampled at data-in time Burst of 2 Read and Write Dual-Range On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs 1.8 V +100/–100 mV core power supply 1.5 V or 1.8 V HSTL Interface Pipelined read operation Fully coherent read and write pipelines ZQ pin for programmable output drive strength Data Valid Pin (QVLD) Support IEEE 1149.1 JTAG-compliant Boundary Scan 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package RoHS-compliant 165-bump BGA package available SigmaDDR-II™ Family Overview The GS81302TT06/11/20/38E are built in compliance with the SigmaDDR-II+ SRAM pinout sta...